1. Technical Field
This disclosure relates to semiconductor devices and more particularly, to an area efficient fuse register that provides electrical programming of on-chip fuses.
2. Description of the Related Art
Memory devices, such as dynamic random access memory devices (DRAM) typically include fuse circuits. Fuses included in these fuse circuits may be employed to activate redundant elements which replace failing cells or components. Fuses may be grouped into two classes, for example, laser fuses and electrical fuses. Laser fuses are blown by a chip-external laser beam which irradiates specific fuses to supply enough energy to blow the fuse. Electrically blowable fuses are blown when a current through the fuses exceeds a threshold causing energy build up to blow the fuse.
One of the major differences between laser fuses and electrical fuses is the way they are addressed (or accessed) in order to blow them. For laser fuses, the laser beam is simply pointed to fuses which are to be blown (i.e., Aaddressing by location@). Contrary to this, electrical fuses must be blown by accessing pins of the chip.
It is desirable for electrical fuses to play an increasing role in higher density memory devices. Considering the large number of fuses typically found on DRAM circuits, the selection of an electrical fuse that should be blown either requires a large amount of decoder circuitry or many address wires on chip, if standard decoding schemes are applied.
Therefore, a need exists for an apparatus which reduces the area overhead caused by the necessity to address electrical fuses on chip.
A circuit for programming electrical fuses, in accordance with the present invention, includes a shift register including a plurality of latches. Each latch has a corresponding switch and a corresponding electrical fuse. A bit generator generates a single bit of a first state and all other bits of a second state. The bit generator propagates the generated bits into the shift register in accordance with a clock signal. Each switch enables conduction through the corresponding electrical fuse in accordance with the generated bits stored in the corresponding latch. A blow voltage line connects to the electrical fuses. The blow voltage line is activated to blow fuses in accordance with programming data such that the electrical fuses are programmed in accordance with the programming data when the single bit of the first state is stored in the latch corresponding to the fuse to be programmed.
In other embodiments, the register may include a shift register and the programming information may be shifted into the shift register. The programming information may be shifted into the shift register in accordance with cycles of a clock signal. The activation event may occur when, the number of clock cycles of the programming information shifted into the shift register equals the number of latches. The programming information may include digital bits and the switch may include a transistor. The switch preferably enables conduction from the blow voltage line to ground through the electrical fuse. The activation event may also occur when the register is full. The circuit may be included in a memory device and the programming information may include results of a redundancy calculation.
Another circuit for programming electrical fuses, in accordance with the present invention, includes a shift register including a plurality of latches, each latch having a corresponding switch and a corresponding electrical fuse. A bit generator generates a single bit of a first state and all other bits of a second state. The bit generator propagates the generated bits into the shift register in accordance with a clock signal. Each switch enables conduction through the corresponding electrical fuse in accordance with the generated bits stored in the corresponding latch. A blow voltage line connects to the electrical fuses, and the blow voltage line is activated to blow fuses in accordance with programming data such that the electrical fuses are programmed in accordance with the programming data when the single bit of the first state is stored in the latch corresponding to the fuse to be programmed.
A fuse latch circuit for programming electrical fuses, in accordance with the present invention, includes a shift register including a plurality of latches, each latch having a corresponding switch and a corresponding electrical fuse, each latch including a serial connection for transferring digital information to an adjacent latch. A bit generator generates a single bit of a first state and all other bits of a second state, and the bit generator propagates the generated bits into the shift register in accordance with a clock signal. Each switch includes a blow transistor having a gate connected to the serial connection for enabling conduction through the corresponding electrical fuse in accordance with the generated bits stored in the corresponding latch. A blow voltage line connects to the electrical fuses, and the blow voltage line is activated to blow fuses in accordance with ordered programming data stored in a memory storage device such that the electrical fuses are programmed in accordance with the ordered programming data when the single bit of the first state is stored in the latch corresponding to the fuse to be programmed. A clock is coupled to the shift register, the bit generator and the memory storage device for providing the clock signal to synchronize the programming data and the generated bits to address the fuses to be programmed.
In other embodiments, the blow voltage line may be enabled by a transistor, and the programming data may be applied to the transistor in accordance with the clock signal. The generated bits are preferably propagated through the shift register in accordance with the clock signal. The switch preferably includes a transistor, and the switch preferably enables conduction from the blow voltage line to ground through the electrical fuse. The circuit may be included in a memory device and the programming data includes results of a redundancy calculation.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.